Configuration for digital-analog conversion of high-frequency digital input signal into carrier-frequency analog output signal

ABSTRACT

A delay device has at least one first delay element and optional additional delay elements connected downstream from the first in a serially consecutive manner. The digital input signal is connected to an input of the first delay element and is connected to an input of a first D/A converter. The output of the first delay element is connected to an input of another D/A converter assigned thereto. The optional additional delay elements each have outputs connected to an input of another D/A converter assigned to the respective delay elements. All D/A converters are combined on the output side in a step-by-step manner so that output signals of all D/A converters form the analog output signal or the device. A specific coefficient is assigned to each D/A converter, and a specific delay time is assigned to each delay element for realizing a filter characteristic.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a 371 of PCT/EP03/08323 filed Jul. 28, 2003.

This application is based on and hereby claims priority to GermanApplication No. 102 27 856.8 filed on 19 Aug. 2002 and EuropeanApplication No. 02018602.9 filed on 19 Aug. 2002, the contents of whichare hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a configuration for the digital-analogconversion of a high-frequency digital input signal into acarrier-frequency analog output signal.

2. Description of the Related Art

Architectures for the generation of a broadband, carrier-frequencyoutput signal are known in which, in a low frequency range, a digitalinput signal is converted into an analog signal using a digital-analogconverter, and then reconverted into the carrier-frequency output signalusing one or more mixing stages.

Furthermore, digital-analog converter architectures are known in which acarrier-frequency output signal is generated from a high-frequencydigital input signal without further frequency conversion. Thecarrier-frequency analog output signal in this case also has unwantedcarrier frequencies in addition to a desired carrier frequency. Theseunwanted carrier frequencies can be caused, for example, by a less thanperfect digital input signal or by various unwanted modulationmechanisms.

In the described architectures, cost-intensive filters with high qualityor mixers with high linearity, which are always configured on the outputend and which must be adjusted to a required carrier frequency range ineach case, are necessary. These must be replaced, at great expense, if achange in carrier frequency range is required.

SUMMARY OF THE INVENTION

An object of this invention is therefore to design a configuration fordigital-analog conversion in such a way that it can be adjusted tovarious carrier frequency ranges without great cost.

A configuration for digital-analog conversion according to one aspect ofthe invention has an integrated filter characteristic, thus eliminatingthe need for cost-intensive mixers or filters at the output end. D/Aconverters are connected parallel to one another and specificcoefficients are assigned to each of the individual D/A converters. Thisenables the configuration to be ideally adjusted to a required carrierfrequency range.

A configuration according to the invention can be adjusted to differentcarrier frequency ranges by modifying the clock frequency of the D/Aconverters accordingly.

According to the invention, it is particularly preferable for a FiniteImpulse Response (FIR) filter characteristic to be realized and/orintegrated into the configuration through the selection of thecoefficients that are specifically assigned to the D/A converters and ofthe delay times that are specifically assigned to the delay elements.The consecutive coefficients correspond to a sampling of an impulseresponse from a filter that has a required filter characteristic. Inthis way the carrier-frequency output signal has a higher spectralpurity compared to a form implemented without filter characteristic.

The FIR filter characteristic integrated according to the invention isscalable using a clock frequency of a clock signal. This may be derivedfrom or identical to the clock frequency of the A/D converters. Sincethe clock frequency usually varies in proportion to the carrierfrequency, the filter characteristic is automatically adjusted in thisinvention.

If there is a change in the required carrier frequency range, the FIRfilter characteristic is reset accordingly via the clock frequency.There is no replacement of hardware components.

If the accuracy and the number of the FIR filter coefficients correspondto the requirements of a new mobile radio standard, then it is possibleto switch frequency range directly via the clock frequency, in whichcase software might be used to implement the switch.

A configuration according to the invention enables expenditure onfilters to be considerably reduced, for any carrier frequency range, byprefiltering. Together with a corresponding power output stage, theelimination of the need for frequency-specific filtering at thetransmitter end makes for high quality.

In particular, quantization noise formed by ΣΔ converters on the inputsignal can easily be suppressed by using a configuration according tothe invention.

The filter function of a configuration according to the invention can beinfluenced by the signal form emitted by each D/A converter per datum orbit. By using a suitable signal form, such as—for example—multiplepulses, which consist of several pulses for each datum, the filterfunction can be improved selectively.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects and advantages of the present invention willbecome more apparent and more readily appreciated from the followingdescription of an exemplary embodiment, taken in conjunction with theaccompanying drawings of which:

FIG. 1 is a block diagram of a configuration for digital-analogconversion according to the invention, and

FIG. 2, by way of comparison with FIG. 1, is a block diagram of anexemplary embodiment of a configuration for digital-analog conversionaccording to the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Reference will now be made in detail to the preferred embodiments of thepresent invention, examples of which are illustrated in the accompanyingdrawings, wherein like reference numerals refer to like elementsthroughout.

FIG. 1 shows a block diagram of a configuration for digital-analogconversion according to the invention.

A high-frequency digital input signal DE arrives at a delay device VZand at a converter device WD.

The delay device VZ has n delay elements VG1, VG2, VG3, . . . , VGn,which are connected in a serially consecutive manner, and with aspecific delay time τl, τ2, 96 3, . . . , τn being assigned to each ofthem. Each individual delay element VG1 to VGn is connected on theoutput side to an output VA1, VA2, VA3, . . . , VAn of the delay deviceVZ. Via each of these outputs VA1 to VAn, a delay signal VS1, VS2, VS3,. . . , VSn, assigned thereto in each case and formed by thecorresponding delay element VG1 to VGn, reaches an input WE1, WE2, WE3,. . . , WEn on the conversion device WD.

The conversion device WD has a total of n+1 D/A converters W0, WI, . . ., Wn, which are arranged in parallel to one another. A first D/Aconverter W0 receives the digital input signal DE, as the input signal,via an input WE0 on the conversion device WD. The other n D/A convertersreceive the delay signals VS1 to VSn, as input signals, viacorrespondingly assigned inputs WE1 to WEn.

A specific coefficient k0, kl, . . . , kn is assigned to each of theindividual n+1 D/A converters WE0 to WEn of the conversion device WD.

The individual D/A converters W0 to Wn are combined on the output side,for example using n adding devices AE1, AE2, . . . , AEn. Using theadding devices AE1 to AEn, n+1 output signals AS0, AS1, . . . , ASn ofthe n+1 D/A converters are added together to form a carrier-frequencyanalog output signal AA.

It should be noted that the digital input signals DE and VS1 to VSn areweighted, during the D/A conversion in the corresponding D/A convertersW0 to Wn, with the respectively assigned coefficients k0 to kn.

These coefficients k0 to kn of the D/A converters W0 to Wn and the delaytimes τ1 to τn of the delay elements VG1 to VGn are defined such that aconfiguration for digital-analog conversion according to the inventionhas a required FIR filter characteristic.

FIG. 2, by way of comparison with FIG. 1, shows an exemplary embodimentof a configuration for digital-analog conversion according to theinvention.

The individual D/A converters W0 to Wn are implemented as I-bit D/Aconverters and the delay elements VG1 to VGn as D latches. Both the D/Aconverters W0 to Wn and the delay elements VG1 to VGn are timed with aclock signal CLK.

The digital input signal DE is connected to the D input of a first Dlatch or of a first delay element VG1. On the output side, the firstdelay element VG1 is connected via its Q output to a D input of the nextdelay element VG2, etc.

Because of the clock signal CLK, the specific delay times τ1 to τnassigned to the individual delay elements VG1 to VGn correspond, asillustrated here, to half of a clock period of the clock signal CLK,which is likewise applied to the D/A converters W0 to Wn. Eachindividual delay element or D latch effects a delay of half of a clockperiod.

However, smaller sections of the clock period of the clock signal CLKmay be used for the delay elements VG1 to VGn. This facilitates a moreprecise adjustment to an impulse response of a required filtercharacteristic. This in turn multiplies the Nyquist frequency of thefilter characteristic and suppresses the alias effect.

The coefficients k0 to kn assigned to the individual D/A converters W0to Wn are set with the help of reference current sources ki*lref (inwhich i=0 to n), which determine the amplitude of the output signals AS0to ASn.

If negative factors are required in the coefficients k0 to kn in orderto realize the FIR filter characteristic, then corresponding outputs areexchanged in the D/A converters affected.

This is shown, by way of example, for the coefficients k2 and kn. Theconnections for the outputs are exchanged in the corresponding D/Aconverters W2 and Wn compared to the D/A converter WI (see detail D).

The output signals AS0 to ASn in the D/A converters W0 to Wn are addedtogether at the same time and form the analog output signal AA.

The high-frequency digital input signal DE can also be in the form of abroadband signal in this invention.

The invention has been described in detail with particular reference topreferred embodiments thereof and examples, but it will be understoodthat variations and modifications can be effected within the spirit andscope of the invention covered by the claims which may include thephrase “at least one of A, B and C” as an alternative expression thatmeans one or more of A, B and C may be used, contrary to the holding inSuperguide v. DIRECTV, 69 USPQ2d 1865 (Fed. Cir. 2004).

1. A configuration for digital-analog conversion of a high-frequencydigital input signal into a carrier-frequency analog output signal,comprising: a delay device having at least one delay element, each delayelement having an input and an output, the input of a first delayelement receiving the high-frequency digital input signal and anyadditional delay elements connected downstream from the first delayelement in a serially consecutive manner; a first D/A converter havingan input receiving the high-frequency digital input signal; and at leastone subsequent D/A converter, each having an input connected to theoutput of a corresponding delay element, all D/A converters controlledwith an identical clock signal and having outputs with a multiple pulsesequence combined in a step-by-step manner to form the analog outputsignal, where a filter characteristic is realized by assigning specificcoefficients to the first and at least one subsequent D/A converters,respectively, and a specific delay time to each delay element, for atotal delay time corresponding to at least part of a clock period of theidentical clock signal such that the filter characteristic isautomatically adjusted if there is a change in carrier frequency rangeof the output signal, thereby improving filter function.
 2. Aconfiguration according to claim 1, wherein the specific coefficientsand the specific delay time of each delay element are selected torealize a Finite Impulse Response filter characteristic.
 3. Aconfiguration according to claim 2, wherein each delay element isconfigured as a D latch timed with the identical clock signal.
 4. Aconfiguration according to claim 3, wherein all D/A converters areconfigured as I-bit D/A converters.
 5. A configuration according toclaim 4, further comprising adding devices connected to the outputs ofall D/A converters for combining thereof.
 6. A configuration accordingto claim 5, wherein the specific delay time assigned to each delayelement is identical.
 7. A configuration according to claim 6, whereinthe high-frequency digital input signal is broadband.